The invention relates to a semiconductor device, and more particularly, to patterning fins of a FinFET semiconductor device.
Interests in multi-gate MOSFETs have significantly increased as the industry continues to demand smaller sized MOSFET devices. One such device that is capable of maintaining industry performance standards at a reduced size is the FinFET.
A conventional FinFET includes one or more fins that are patterned on a substrate, such as a silicon-on-insulator (SOI). For example, a conventional sidewall image transfer (SIT) process can be used to form a dense array of fins, which extend into the source/drain (S/D) regions of the FinFET. Conventional FinFET fabrication requires an epitaxy (EPI) process to merge the fins formed in the S/D regions. However, this process causes undesirable gaps between the fins, and may also create source/drain shorting issues at the gate line ends if the EPI process is not properly controlled.
Moreover, conventional fabrication processes perform gate patterning for forming a gate after forming the fins. The gate patterning utilizes hardmasks, and performs additional spacer etching processes. However, the fins may be inadvertently eroded during the gate and spacer etching processes.